1217 search results - page 162 / 244 » Uncertainty-aware circuit optimization |
117
Voted
DAC
2004
ACM
16 years 4 months ago
2004
ACM
We present a set of techniques for placement-coupled, timingdriven logic replication. Two components are at the core of the approach. First is an algorithm for optimal timingdrive...
133
Voted
DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
In this paper, a simulation-based synthesis tool, AMIGO, for analog cell sizing is presented. AMIGO is based upon genetic optimization techniques adapted to circuit sizing. A fram...
130
Voted
ISQED
2003
IEEE
15 years 9 months ago
2003
IEEE
In this paper, we propose a new physical synthesis methodology, PDL, which relaxes the timing constraints to obtain best optimality in terms of layout quality and timing quality. ...
136
click to vote
DATE
2002
IEEE
15 years 8 months ago
2002
IEEE
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
108
Voted
ISCAS
2005
IEEE
15 years 9 months ago
2005
IEEE
-- Timing optimization is an important goal of global routing in deep submicron era. To guarantee the timing performance of the circuit, merely adopting topology optimization becom...