1217 search results - page 163 / 244 » Uncertainty-aware circuit optimization |
127
Voted
ICIP
2008
IEEE
16 years 5 months ago
2008
IEEE
The continual shrinkage of minimum feature size in integrated circuit (IC) fabrication incurs more and more serious distortion in the optical lithography process, generating circu...
103
Voted
DAC
1999
ACM
16 years 4 months ago
1999
ACM
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
98
Voted
ICCD
2008
IEEE
16 years 19 days ago
2008
IEEE
—This paper compares the energy-delay tradeoff curves of 32-bit static barrel and funnel shifters. The Stanford Circuit Optimization Tool (SCOT) is used to determine best transis...
109
Voted
ICCD
2003
IEEE
16 years 18 days ago
2003
IEEE
We discuss the compaction of independent test sequences for sequential circuits. Our first contribution is the formulation of this problem as an integer program, which we then so...
111
Voted
DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
—Redundancy Addition and Removal (RAR) is a restructuring technique used in the synthesis and optimization of logic designs. It can remove an existing target wire and add an alte...