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» Uncertainty-aware circuit optimization
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126
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GLVLSI
2009
IEEE
112views VLSI» more  GLVLSI 2009»
15 years 10 months ago
Simultaneous shield and repeater insertion
Resource based optimization for high performance integrated circuits is presented. The methodology is applied to simultaneous shield and repeater insertion, resulting in minimum c...
Renatas Jakushokas, Eby G. Friedman
124
Voted
ISQED
2006
IEEE
94views Hardware» more  ISQED 2006»
15 years 9 months ago
System-Level SRAM Yield Enhancement
It is well known that SRAM constitutes a large portion of modern integrated circuits, with 80% or more of the total transistors being dedicated to SRAM in a typical processor or S...
Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park...
128
Voted
ISVLSI
2006
IEEE
126views VLSI» more  ISVLSI 2006»
15 years 9 months ago
QUKU: A Two-Level Reconfigurable Architecture
FPGAs have been used for prototyping of ASICs, for low-volume ASIC replacement and for systems requiring in-field hardware upgrades. However, the potential to use dynamic reconfig...
Sunil Shukla, Neil W. Bergmann, Jürgen Becker
106
Voted
GLVLSI
2005
IEEE
199views VLSI» more  GLVLSI 2005»
15 years 9 months ago
Interconnect delay minimization through interlayer via placement in 3-D ICs
The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable vertical through via lo...
Vasilis F. Pavlidis, Eby G. Friedman
111
Voted
ISCAS
2005
IEEE
119views Hardware» more  ISCAS 2005»
15 years 9 months ago
Analysis of power consumption in VLSI global interconnects
Abstract— The analysis of effects induced by interconnects become increasingly important as the scale of process technologies steadily shrinks. While most analyses focus on the t...
Youngsoo Shin, Hyung-Ock Kim