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129
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GLVLSI
2009
IEEE
167views VLSI» more  GLVLSI 2009»
15 years 10 months ago
Dual-threshold pass-transistor logic design
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...
Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. ...
127
Voted
GLVLSI
2007
IEEE
187views VLSI» more  GLVLSI 2007»
15 years 10 months ago
DAG based library-free technology mapping
This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
Felipe S. Marques, Leomar S. da Rosa Jr., Renato P...
121
Voted
ISQED
2007
IEEE
106views Hardware» more  ISQED 2007»
15 years 10 months ago
Passive Modeling of Interconnects by Waveform Shaping
In this paper, we propose a new approach to enforcing the passivity of a reduced system of general passive linear time invariant circuits. Instead of making the reduced models pas...
Boyuan Yan, Pu Liu, Sheldon X.-D. Tan, Bruce McGau...
94
Voted
ICALP
2007
Springer
15 years 10 months ago
Approximation by DNF: Examples and Counterexamples
Say that f : {0, 1}n → {0, 1} -approximates g : {0, 1}n → {0, 1} if the functions disagree on at most an fraction of points. This paper contains two results about approximatio...
Ryan O'Donnell, Karl Wimmer
135
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ASPDAC
2006
ACM
110views Hardware» more  ASPDAC 2006»
15 years 9 months ago
Switching-activity driven gate sizing and Vth assignment for low power design
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Pr...
Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang