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» Uncertainty-aware circuit optimization
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FPL
2006
Springer
137views Hardware» more  FPL 2006»
15 years 1 months ago
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations
Both custom IC and FPGA designs in the nanometer regime suffer from process variations. But different from custom ICs, FPGAs' programmability offers a unique design freedom t...
Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton
AHS
2006
IEEE
127views Hardware» more  AHS 2006»
15 years 1 months ago
Using Hardware-Based Particle Swarm Method for Dynamic Optimization of Adaptive Array Antennas
The following article describes and discusses the suitability of the particle swarm optimization (PSO) for the employment with blind adaptation of the directional characteristic o...
Gabriella Kókai, Tonia Christ, Hans Holm Fr...
ISPD
1997
ACM
142views Hardware» more  ISPD 1997»
15 years 1 months ago
Minimization of chip size and power consumption of high-speed VLSI buffers
In this paper, we study optimal bu er design in high-performance VLSI systems. Speci cally, we design a bu er for a given load such that chip area and power dissipation are minima...
D. Zhou, X. Y. Liu
81
Voted
VLSID
1999
IEEE
91views VLSI» more  VLSID 1999»
15 years 1 months ago
Timed Circuit Synthesis Using Implicit Methods
The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorp...
Robert Thacker, Wendy Belluomini, Chris J. Myers
DAC
1997
ACM
15 years 1 months ago
Developing a Concurrent Methodology for Standard-Cell Library Generation
Abstract - This paper describes the development of a concurrent methodology for standard cell library generation. Use of a novel physical design automation method enables a high de...
Donald G. Baltus, Thomas Varga, Robert C. Armstron...