1217 search results - page 17 / 244 » Uncertainty-aware circuit optimization |
EUROGP
2008
Springer
14 years 11 months ago
2008
Springer
A new class of FPGA-based accelerators is presented for Cartesian Genetic Programming (CGP). The accelerators contain a genetic engine which is reused in all applications. Candidat...
125
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ISPD
2012
ACM
13 years 5 months ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
ICCAD
1994
IEEE
15 years 1 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
95
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EH
2004
IEEE
15 years 1 months ago
2004
IEEE
Field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. One of the necessary requirements to effectively utilize ...
102
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AIA
2007
14 years 11 months ago
2007
Designers aim at fast but low-power consuming integrated circuits. Since high processing speed always comes with high energy demands, the literature provides several ways to reduc...