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» Uncertainty-aware circuit optimization
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ASPDAC
2009
ACM
161views Hardware» more  ASPDAC 2009»
15 years 5 months ago
Risk aversion min-period retiming under process variations
— Recent advances in statistical timing analysis (SSTA) achieve great success in computing arrival times under variations by extending sum and maximum operations to random variab...
Jia Wang, Hai Zhou
DATE
2008
IEEE
111views Hardware» more  DATE 2008»
15 years 5 months ago
Incremental Criticality and Yield Gradients
— Criticality and yield gradients are two crucial diagnostic metrics obtained from Statistical Static Timing Analysis (SSTA). They provide valuable information to guide timing op...
Jinjun Xiong, Vladimir Zolotov, Chandu Visweswaria...
ISQED
2005
IEEE
76views Hardware» more  ISQED 2005»
15 years 4 months ago
Technology Mapping for Reliability Enhancement in Logic Synthesis
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
Zhaojun Wo, Israel Koren
SAMOS
2004
Springer
15 years 4 months ago
A Novel Data-Path for Accelerating DSP Kernels
A high-performance data-path to implement DSP kernels is proposed in this paper. The data-path is based on a flexible, universal, and regular component to optimally exploiting both...
Michalis D. Galanis, George Theodoridis, Spyros Tr...
GLVLSI
2010
IEEE
156views VLSI» more  GLVLSI 2010»
15 years 4 months ago
A multi-level approach to reduce the impact of NBTI on processor functional units
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
Taniya Siddiqua, Sudhanva Gurumurthi