1217 search results - page 192 / 244 » Uncertainty-aware circuit optimization |
DATE
2008
IEEE
15 years 5 months ago
2008
IEEE
The wiring effort and thus, the routability of electronic designs such as printed circuit boards, multi chip modules and single chip modules largely depends on the assignment of s...
102
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CEC
2007
IEEE
15 years 5 months ago
2007
IEEE
— Determining the optimal topology of a graph is pertinent to many domains, as graphs can be used to model a variety of systems. Evolutionary algorithms constitute a popular opti...
103
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DAC
2003
ACM
16 years 6 days ago
2003
ACM
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
DAC
2003
ACM
16 years 6 days ago
2003
ACM
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
DAC
2004
ACM
16 years 6 days ago
2004
ACM
With process scaling, leakage power reduction has become one of the most important design concerns. Multi-threshold techniques have been used to reduce runtime leakage power witho...