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» Uncertainty-aware circuit optimization
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DATE
2007
IEEE
130views Hardware» more  DATE 2007»
15 years 5 months ago
A novel criticality computation method in statistical timing analysis
Abstract— The impact of process variations increases as technology scales to nanometer region. Under large process variations, the path and arc/node criticality [18] provide effe...
Feng Wang 0004, Yuan Xie, Hai Ju
FPGA
2007
ACM
106views FPGA» more  FPGA 2007»
15 years 5 months ago
A synthesizable datapath-oriented embedded FPGA fabric
We present an architecture for a synthesizable datapathoriented Field Programmable Gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a Systemon-...
Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai ...
DAC
2006
ACM
15 years 5 months ago
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper, a predictive model is developed for the deg...
Rakesh Vattikonda, Wenping Wang, Yu Cao
ASPDAC
2005
ACM
127views Hardware» more  ASPDAC 2005»
15 years 4 months ago
Clock network minimization methodology based on incremental placement
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, ...
ISPD
2005
ACM
140views Hardware» more  ISPD 2005»
15 years 4 months ago
Are floorplan representations important in digital design?
Research in floorplanning and block-packing has generated a variety of data structures to represent spatial configurations of circuit modules. Much of this work focuses on the g...
Hayward H. Chan, Saurabh N. Adya, Igor L. Markov