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» Uncertainty-aware circuit optimization
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FPGA
2005
ACM
80views FPGA» more  FPGA 2005»
15 years 4 months ago
Simultaneous timing-driven placement and duplication
Logic duplication is an effective method for improving circuit performance. In this paper we present an algorithm named SPD that performs simultaneous placement and duplication to...
Gang Chen, Jason Cong
SIGIR
2003
ACM
15 years 4 months ago
HAT: a hardware assisted TOP-DOC inverted index component
A novel Hardware Assisted Top-Doc (HAT) component is disclosed. HAT is an optimized content indexing device based on a modified inverted index structure. HAT accommodates patterns...
S. Kagan Agun, Ophir Frieder
GECCO
2003
Springer
158views Optimization» more  GECCO 2003»
15 years 4 months ago
Active Control of Thermoacoustic Instability in a Model Combustor with Neuromorphic Evolvable Hardware
Continuous Time Recurrent Neural Networks (CTRNNs) have previously been proposed as an enabling paradigm for evolving analog electrical circuits to serve as controllers for physica...
John C. Gallagher, Saranyan Vigraham
VLSID
2002
IEEE
97views VLSI» more  VLSID 2002»
15 years 4 months ago
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement
Power supply noise is a strong function of the switching activities of the circuit modules. Peak power supply noise can be significantly reduced by judiciously arranging the modu...
Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
TCS
2002
14 years 11 months ago
Some permutation routing algorithms for low-dimensional hypercubes
Oblivious permutation routing in binary d-cubes has been well studied in the literature. In a permutation routing, each node initially contains a packet with a destination such th...
Frank K. Hwang, Y. C. Yao, Bhaskar DasGupta