1217 search results - page 196 / 244 » Uncertainty-aware circuit optimization |
110
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ICCAD
2009
IEEE
14 years 9 months ago
2009
IEEE
Process and environmental variations continue to present significant challenges to designers of high-performance integrated circuits. In the past few years, while much research has...
JCNS
2010
14 years 6 months ago
2010
The early processing of sensory information by neuronal circuits often includes a reshaping of activity patterns that may facilitate the further processing of stimulus representat...
DAC
2009
ACM
16 years 6 days ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
106
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ICCAD
2009
IEEE
14 years 9 months ago
2009
IEEE
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major design challenge. Threshold voltage (vt) assignment has been extensively studied, du...
JCO
2011
14 years 6 months ago
2011
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...