1217 search results - page 199 / 244 » Uncertainty-aware circuit optimization |
ISQED
2010
IEEE
15 years 6 months ago
2010
IEEE
—Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology optio...
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NOCS
2008
IEEE
15 years 5 months ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
MEMOCODE
2006
IEEE
15 years 5 months ago
2006
IEEE
The theory of latency-insensitive design (LID) was recently invented to cope with the time closure problem in otherwise synchronous circuits and programs. The idea is to allow the...
ISPD
2004
ACM
15 years 4 months ago
2004
ACM
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...
COCO
2004
Springer
15 years 4 months ago
2004
Springer
This paper develops new relationships between resource-bounded dimension, entropy rates, and compression. New tools for calculating dimensions are given and used to improve previo...