1217 search results - page 19 / 244 » Uncertainty-aware circuit optimization |
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
This paper presents a multiple-FPGA-based experimentation board. The problem to be solved is that of implementing a circuit into a set of FPGAs. This board provides a hardware env...
73
Voted
VLSI
2005
Springer
15 years 2 months ago
2005
Springer
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
CEC
2009
IEEE
15 years 4 months ago
2009
IEEE
— Polymorphic digital circuits contain ordinary and polymorphic gates. In the past, Cartesian Genetic Programming (CGP) has been applied to synthesize polymorphic circuits at the...
ICCAD
2000
IEEE
15 years 1 months ago
2000
IEEE
ct Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particul...
JUCS
2006
14 years 9 months ago
2006
: The paper concerns the design of evolutionary algorithms and pattern search methods on two circuit design problems: the multi-objective optimization of an Operational Transconduc...