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» Uncertainty-aware circuit optimization
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ISCAS
2005
IEEE
147views Hardware» more  ISCAS 2005»
15 years 4 months ago
A two-chip, 4-MHz, microelectromechanical reference oscillator
— The paper describes a 4-MHz temperature compensated reference oscillator based on a capacitive silicon micro-mechanical resonator. The design of the resonator has been optimize...
Krishnakumar Sundaresan, Paul S. Ho, Siavash Pourk...
83
Voted
FPL
2005
Springer
115views Hardware» more  FPL 2005»
15 years 4 months ago
Statistical Power Estimation for FPGA
This article presents a power estimation tool integrated with an FPGA design flow. It is able to estimate total and individual-node average power consumption for combinational blo...
Elias Todorovich, Fabian Angarita, Javier Valls, E...
61
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GECCO
2005
Springer
152views Optimization» more  GECCO 2005»
15 years 4 months ago
Multi-level genetic algorithm (MLGA) for the construction of clock binary tree
The clock signal and clock skew become more and more important for the circuit performance. Since there are salient shortcomings in the conventional topology construction algorith...
Guofang Nan, Minqiang Li, Jisong Kou
FPL
2004
Springer
113views Hardware» more  FPL 2004»
15 years 4 months ago
An Evolvable Hardware Tutorial
Abstract. Evolvable Hardware (EHW) is a scheme - inspired by natural evolution, for automatic design of hardware systems. By exploring a large design search space, EHW may find so...
Jim Torresen
GECCO
2004
Springer
211views Optimization» more  GECCO 2004»
15 years 4 months ago
Node-Depth Encoding for Evolutionary Algorithms Applied to Network Design
Network design involves several areas of engineering and science. Computer networks, electrical circuits, transportation problems, and phylogenetic trees are some examples. In gene...
Alexandre C. B. Delbem, André Carlos Ponce ...