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» Uncertainty-aware circuit optimization
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ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
15 years 1 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
JIRS
2007
229views more  JIRS 2007»
14 years 9 months ago
Unmanned Vehicle Controller Design, Evaluation and Implementation: From MATLAB to Printed Circuit Board
A detailed step-by-step approach is presented to optimize, standardize, and automate the process of unmanned vehicle controller design, evaluation, validation and verification, fol...
Daniel Ernst, Kimon P. Valavanis, Richard Garcia, ...
ATS
2004
IEEE
116views Hardware» more  ATS 2004»
15 years 1 months ago
Testing for Missing-Gate Faults in Reversible Circuits
Logical reversibility occurs in low-power applications and is an essential feature of quantum circuits. Of special interest are reversible circuits constructed from a class of rev...
John P. Hayes, Ilia Polian, Bernd Becker
EVOW
2000
Springer
15 years 1 months ago
Prediction of Power Requirements for High-Speed Circuits
Modern VLSI design methodologies and manufacturing technologies are making circuits increasingly fast. The quest for higher circuit performance and integration density stems from f...
Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Re...
DATE
1998
IEEE
73views Hardware» more  DATE 1998»
15 years 1 months ago
On Removing Multiple Redundancies in Combinational Circuits
1 Redundancy removal is an important step in combinational logic optimization. After a redundant wire is removed, other originally redundant wires may become irredundant, and some ...
David Ihsin Cheng