1217 search results - page 210 / 244 » Uncertainty-aware circuit optimization |
214
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Publication
he significant increase in the available computational power that took place in recent decades has been accompanied by a growing interest in the application of the evolutionary ap...
DAC
2005
ACM
16 years 1 months ago
2005
ACM
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...
88
Voted
ICCAD
2005
IEEE
15 years 9 months ago
2005
IEEE
Abstract— We present in this paper a new interconnect-driven multilevel floorplanning, called IMF, to handle large-scale building-module designs. Unlike the traditional multilev...
115
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ISPD
2009
ACM
15 years 7 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
78
Voted
DAC
2005
ACM
16 years 1 months ago
2005
ACM
We present a new methodology which takes into consideration the effect of Within-Die (WID) process variations on a low-voltage parallel system. We show that in the presence of pro...