1217 search results - page 211 / 244 » Uncertainty-aware circuit optimization |
92
Voted
VLSID
2002
IEEE
15 years 11 months ago
2002
IEEE
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
69
Voted
ICCD
2004
IEEE
15 years 8 months ago
2004
IEEE
The increasing clock frequencies in high-end industrial circuits bring new routing challenges that can not be handled by traditional algorithms. An important design automation pro...
ICCAD
2004
IEEE
15 years 8 months ago
2004
IEEE
Traditional timing-driven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the ...
ICCAD
2004
IEEE
15 years 8 months ago
2004
IEEE
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...
ICCAD
2002
IEEE
15 years 8 months ago
2002
IEEE
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system archite...