1217 search results - page 212 / 244 » Uncertainty-aware circuit optimization |
57
Voted
ICCAD
2001
IEEE
15 years 6 months ago
2001
IEEE
In deep submicron VLSI circuits, interconnect reliability due to electromigration and thermal effects is fast becoming a serious design issue particularly for long signal lines. T...
ICCAD
2001
IEEE
15 years 6 months ago
2001
IEEE
As system integration evolves and tighter design constraints must be met, it becomes necessary to account for the non-ideal behavior of all the elements in a system. Certain devic...
92
Voted
ISPD
2010
ACM
15 years 4 months ago
2010
ACM
Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain di...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—Due to increasing complexity of design interactions between the chip, package and PCB, it is essential to consider them at the same time. Specifically the finger/pad locations...
63
Voted
ISQED
2008
IEEE
15 years 3 months ago
2008
IEEE
– As silicon technology scales, we can integrate more and more circuits on a single chip, which means more I/Os are needed in modern designs. The flip-chip technology which was ...