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» Uncertainty-aware circuit optimization
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85
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ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
15 years 2 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
72
Voted
ISPD
2003
ACM
103views Hardware» more  ISPD 2003»
15 years 2 months ago
An integrated floorplanning with an efficient buffer planning algorithm
Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate t...
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, ...
CC
2003
Springer
15 years 2 months ago
Early Control of Register Pressure for Software Pipelined Loops
Abstract. The register allocation in loops is generally performed after or during the software pipelining process. This is because doing a conventional register allocation at firs...
Sid Ahmed Ali Touati, Christine Eisenbeis
EVOW
2003
Springer
15 years 2 months ago
GAME-HDL: Implementation of Evolutionary Algorithms Using Hardware Description Languages
Evolutionary Algorithms (EAs) have been proposed as a very powerful heuristic optimization technique to solve complex problems. Many case studies have shown that they work very eff...
Rolf Drechsler, Nicole Drechsler
HICSS
2002
IEEE
128views Biometrics» more  HICSS 2002»
15 years 2 months ago
Developing a Flexible System-Modeling Environment for Engineers
We are developing a module-oriented, multiphysics, mixed-fidelity system simulation environment that will enable engineers to rapidly analyze the performance of a system and to o...
David R. Gardner, Joseph P. Castro, Paul N. Demmie...