1217 search results - page 21 / 244 » Uncertainty-aware circuit optimization |
DAC
2005
ACM
14 years 11 months ago
2005
ACM
Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient ...
69
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CDES
2006
14 years 11 months ago
2006
Abstract--This paper describes an architecture of FPGAlike fabric for future hybrid "CMOL" circuits. Such circuits will combine a semiconductor-transistor (CMOS) stack an...
ICCAD
1995
IEEE
15 years 1 months ago
1995
IEEE
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
IWANN
1995
Springer
15 years 1 months ago
1995
Springer
This paper presents a comparative analysis of neural networks, simulated annealing, and genetic algorithms in the determination of input patterns for testing analog circuits. The ...
DAC
2011
ACM
13 years 9 months ago
2011
ACM
SRAM design has been a major challenge for nanoscale manufacturing technology. We propose a new bit cell repair scheme for designing maximum-information memory system (MIMS). Unli...