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» Uncertainty-aware circuit optimization
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COCO
2005
Springer
99views Algorithms» more  COCO 2005»
15 years 3 months ago
On the Complexity of Succinct Zero-Sum Games
We study the complexity of solving succinct zero-sum games, i.e., the games whose payoff matrix M is given implicitly by a Boolean circuit C such that M(i, j) = C(i, j). We comple...
Lance Fortnow, Russell Impagliazzo, Valentine Kaba...
ISLPED
2004
ACM
102views Hardware» more  ISLPED 2004»
15 years 2 months ago
Microarchitectural power modeling techniques for deep sub-micron microprocessors
The need to perform early design studies that combine architectural simulation with power estimation has become critical as power has become a design constraint whose importance h...
Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M...
FPL
2009
Springer
86views Hardware» more  FPL 2009»
15 years 2 months ago
Improving logic density through synthesis-inspired architecture
We leverage properties of the logic synthesis netlist to define both a logic element architecture and an associated technology mapping algorithm that together provide improved lo...
Jason Helge Anderson, Qiang Wang
TCAD
2010
97views more  TCAD 2010»
14 years 4 months ago
Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages
Abstract--This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done w...
Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li...
DAC
2009
ACM
15 years 10 months ago
Event-driven gate-level simulation with GP-GPUs
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely ? from high-level descriptions down to gate-level ones ?...
Debapriya Chatterjee, Andrew DeOrio, Valeria Berta...