1217 search results - page 224 / 244 » Uncertainty-aware circuit optimization |
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the red...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
In this paper, we propose the first wire density driven global routing that considers CMP variation and timing. To enable CMP awareness during global routing, we propose a compac...
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
— Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock t...
ICCAD
2004
IEEE
15 years 6 months ago
2004
IEEE
Power is an increasingly important design constraint for FPGAs in nanometer technologies. Because interconnect power is dominant in FPGAs, we design Vdd-programmable interconnect ...
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FPGA
2010
ACM
15 years 6 months ago
2010
ACM
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...