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» Uncertainty-aware circuit optimization
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ITC
2002
IEEE
114views Hardware» more  ITC 2002»
15 years 2 months ago
Scan Power Reduction Through Test Data Transition Frequency Analysis
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
ICCAD
2000
IEEE
124views Hardware» more  ICCAD 2000»
15 years 1 months ago
A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis
— Memory is one of the most important components to be optimized in the several phases of the synthesis process. ioral synthesis, a memory is viewed as an abstract construct whic...
Gernot Koch, Taewhan Kim, Reiner Genevriere
ISLPED
1999
ACM
236views Hardware» more  ISLPED 1999»
15 years 1 months ago
Modeling and automating selection of guarding techniques for datapath elements
While guarded evaluation has proven an effective energy saving technique in arithmetic circuits, good methodologies do not exist for determining when and how to guard for maximal ...
William E. Dougherty, Donald E. Thomas
HEURISTICS
2002
99views more  HEURISTICS 2002»
14 years 9 months ago
Parallelizing Tabu Search on a Cluster of Heterogeneous Workstations
In this paper, we present the parallelization of tabu search on a network of workstations using PVM. Two parallelization strategies are integrated: functional decomposition strate...
Ahmad A. Al-Yamani, Sadiq M. Sait, Habib Youssef, ...
88
Voted
AI
1999
Springer
14 years 9 months ago
Learning by Discovering Concept Hierarchies
We present a new machine learning method that, given a set of training examples, induces a definition of the target concept in terms of a hierarchy of intermediate concepts and th...
Blaz Zupan, Marko Bohanec, Janez Demsar, Ivan Brat...