1217 search results - page 235 / 244 » Uncertainty-aware circuit optimization |
ICCAD
2008
IEEE
15 years 8 months ago
2008
IEEE
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
82
Voted
DAC
2007
ACM
16 years 1 days ago
2007
ACM
In this paper, we present a new multi-packing tree (MP-tree) representation for macro placement to handle mixed-size designs. Based on binary trees, the MP-tree is very efficient,...
DAC
2002
ACM
16 years 16 hour ago
2002
ACM
We have developed a generic integer linear programming(ILP)based engineering change(EC) methodology. The EC methodology has three components: enabling, fast, and preserving. Enabl...
99
Voted
DAC
2005
ACM
16 years 16 hour ago
2005
ACM
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
DAC
2006
ACM
16 years 15 hour ago
2006
ACM
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures. To improve via yield and reliability, redundant-via insertion is a highl...