1217 search results - page 24 / 244 » Uncertainty-aware circuit optimization |
DAC
2011
ACM
13 years 9 months ago
2011
ACM
This paper studies TSV-to-TSV coupling in 3D ICs. A full-chip SI analysis flow is proposed based on the proposed coupling model. Analysis results show that TSVs cause significan...
ETS
2010
IEEE
14 years 10 months ago
2010
IEEE
It was shown in the past that ATPG based on the Boolean Satisfiability problem is a beneficial complement to traditional ATPG techniques. Its advantages can be observed especially ...
FPGA
2006
ACM
15 years 1 months ago
2006
ACM
This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...
TCAD
2008
14 years 9 months ago
2008
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
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ISQED
2010
IEEE
14 years 11 months ago
2010
IEEE
Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint. Existing methods force designers to either resort...