1217 search results - page 28 / 244 » Uncertainty-aware circuit optimization |
100
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TVLSI
2008
14 years 11 months ago
2008
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
ISCAS
2007
IEEE
15 years 5 months ago
2007
IEEE
— Employing multiple supply voltages (multi-VDD) is attractive for reducing the power consumption without sacrificing the speed of an integrated circuit (IC). In order to transfe...
ISLPED
1995
ACM
15 years 2 months ago
1995
ACM
A dual-rail CMOS adiabatic switching circuit approach is described which follows the electroid model of Hall. These circuits can operate in either the retractile cascade or the re...
107
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DATE
2005
IEEE
15 years 4 months ago
2005
IEEE
Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and suppl...
ISVLSI
2002
IEEE
15 years 4 months ago
2002
IEEE
Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be re...