Sciweavers

1217 search results - page 29 / 244
» Uncertainty-aware circuit optimization
Sort
View
IPPS
1998
IEEE
15 years 3 months ago
Meta-heuristics for Circuit Partitioning in Parallel Test Generation
In this communication Simulated Annealing and Genetic Algorithms, are applied to the graph partitioning problem. These techniques mimic processes in statistical mechanics and biol...
Consolación Gil, Julio Ortega, Antonio F. D...
ASPDAC
2007
ACM
136views Hardware» more  ASPDAC 2007»
15 years 3 months ago
Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies
The scaling of CMOS technology into the nanometer era enables the fabrication of highly integrated systems, which increasingly contain analog and/or RF parts. However, scaling into...
Georges G. E. Gielen
ASPDAC
2005
ACM
92views Hardware» more  ASPDAC 2005»
15 years 1 months ago
Partitioning and placement for buildable QCA circuits
— Quantum-dot Cellular Automata (QCA) is a novel computing mechanism that can represent binary information based on spatial distribution of electron charge configuration in chem...
Ramprasad Ravichandran, Michael T. Niemier, Sung K...
PADS
1996
ACM
15 years 3 months ago
Conservative Circuit Simulation on Shared-Memory Multiprocessors
We investigate conservative parallel discrete event simulations for logical circuits on shared-memory multiprocessors. For a first estimation of the possible speedup, we extend th...
Jörg Keller, Thomas Rauber, Bernd Rederlechne...
110
Voted
IFIP
1992
Springer
15 years 3 months ago
Controller Implementation by Communicating Asynchronous Sequential Circuits Generated from a Petri Net Specification of Required
This paper presents a completely systematic design procedure for asynchronous controllers. The initial step is the construction of a signal transition graph (STG, an interpreted P...
Jochen Beister, Ralf Wollowski