1217 search results - page 35 / 244 » Uncertainty-aware circuit optimization |
105
Voted
EUROGP
2004
Springer
15 years 4 months ago
2004
Springer
Abstract. In this paper we propose an approach to Genetic Programming based on code reuse and we test it in the design of combinational logic circuits at the gate-level. The circui...
74
Voted
DAC
2009
ACM
16 years 3 days ago
2009
ACM
This paper describes a function-based timing-driven optimization technique for the synthesis of multi-level logic circuits. Motivated by the principles of parallel prefix computat...
EURODAC
1994
IEEE
15 years 3 months ago
1994
IEEE
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
VLSID
1999
IEEE
15 years 3 months ago
1999
IEEE
This paper provides a theoretical basis for eliminating or reducing the energy consumption due to transients in a synchronous digital circuit. The transient energy is minimized wh...
ASPDAC
2008
ACM
15 years 28 days ago
2008
ACM
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...