Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequent...
We describe a working implementation of leveled homomorphic encryption (without bootstrapping) that can evaluate the AES-128 circuit in three different ways. One variant takes und...
- This paper presents an optimal algorithm for solving the problem of simultaneous fanout optimization and routing tree construction for an ordered set of critical sinks. The algor...
In this paper we present a method for FPGA datapath precision optimization subject to user-defined area and error constraints. This work builds upon our previous research [1] which...