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TCAD
2008
93views more  TCAD 2008»
14 years 11 months ago
Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion
Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
143
Voted
ASPDAC
2011
ACM
297views Hardware» more  ASPDAC 2011»
14 years 2 months ago
CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits
3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequent...
Shashikanth Bobba, Ashutosh Chakraborty, Olivier T...
CRYPTO
2012
Springer
234views Cryptology» more  CRYPTO 2012»
13 years 1 months ago
Homomorphic Evaluation of the AES Circuit
We describe a working implementation of leveled homomorphic encryption (without bootstrapping) that can evaluate the AES-128 circuit in three different ways. One variant takes und...
Craig Gentry, Shai Halevi, Nigel P. Smart
ICCAD
1998
IEEE
81views Hardware» more  ICCAD 1998»
15 years 3 months ago
A simultaneous routing tree construction and fanout optimization algorithm
- This paper presents an optimal algorithm for solving the problem of simultaneous fanout optimization and routing tree construction for an ordered set of critical sinks. The algor...
Amir H. Salek, Jinan Lou, Massoud Pedram
FCCM
2004
IEEE
98views VLSI» more  FCCM 2004»
15 years 2 months ago
Automated Least-Significant Bit Datapath Optimization for FPGAs
In this paper we present a method for FPGA datapath precision optimization subject to user-defined area and error constraints. This work builds upon our previous research [1] which...
Mark L. Chang, Scott Hauck