1217 search results - page 42 / 244 » Uncertainty-aware circuit optimization |
ICCAD
1998
IEEE
15 years 3 months ago
1998
IEEE
This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm w...
ICIC
2007
Springer
15 years 27 days ago
2007
Springer
The buck converter is one of DC/DC converters that are often used as power supplies. This paper presents parameter tuning methods to obtain circuit element values for the buck conv...
103
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DAC
1997
ACM
15 years 2 months ago
1997
ACM
We propose a methodology for applying gate-level logic transformations to optimize power in digital circuits. Statistically simulated[14] switching information, gate delays, signa...
97
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UAI
1996
15 years 13 days ago
1996
In this paper we propose a family of algorithms combining treeclustering with conditioning that trade space for time. Such algorithms are useful for reasoning in probabilistic and...
91
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ICCAD
2009
IEEE
14 years 9 months ago
2009
IEEE
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs ...