1217 search results - page 42 / 244 » Uncertainty-aware circuit optimization |
118
Voted
ICCAD
1998
IEEE
15 years 5 months ago
1998
IEEE
This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm w...
99
Voted
ICIC
2007
Springer
15 years 2 months ago
2007
Springer
The buck converter is one of DC/DC converters that are often used as power supplies. This paper presents parameter tuning methods to obtain circuit element values for the buck conv...
125
Voted
DAC
1997
ACM
15 years 4 months ago
1997
ACM
We propose a methodology for applying gate-level logic transformations to optimize power in digital circuits. Statistically simulated[14] switching information, gate delays, signa...
110
Voted
UAI
1996
15 years 2 months ago
1996
In this paper we propose a family of algorithms combining treeclustering with conditioning that trade space for time. Such algorithms are useful for reasoning in probabilistic and...
105
Voted
ICCAD
2009
IEEE
14 years 10 months ago
2009
IEEE
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs ...