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» Uncertainty-aware circuit optimization
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ICCAD
2003
IEEE
115views Hardware» more  ICCAD 2003»
15 years 8 months ago
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit tim...
Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda
ISPD
1999
ACM
98views Hardware» more  ISPD 1999»
15 years 3 months ago
Towards synthetic benchmark circuits for evaluating timing-driven CAD tools
For the development and evaluation of CAD-tools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable cha...
Dirk Stroobandt, Peter Verplaetse, Jan Van Campenh...
77
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ASPDAC
2007
ACM
96views Hardware» more  ASPDAC 2007»
15 years 3 months ago
Hierarchical Optimization Methodology for Wideband Low Noise Amplifiers
In this paper, we present a systematic synthesis methodology for fully integrated wideband low noise amplifiers that simultaneously optimizes impedance matching, noise figure, and ...
Arthur Nieuwoudt, Tamer Ragheb, Yehia Massoud
WSC
2007
15 years 1 months ago
Optimizing time warp simulation with reinforcement learning techniques
Adaptive Time Warp protocols in the literature are usually based on a pre-defined analytic model of the system, expressed as a closed form function that maps system state to cont...
Jun Wang, Carl Tropper
72
Voted
CEC
2003
IEEE
15 years 4 months ago
MEH: modular evolvable hardware for designing complex circuits
Evolvable hardware adjusts oneself to changeable environments by self-organizing the circuit. Due to its high productivity and creativity for designing circuit, it is widely invest...
Jin-Hyuk Hong, Sung-Bae Cho