1217 search results - page 46 / 244 » Uncertainty-aware circuit optimization |
ISPD
2000
ACM
15 years 3 months ago
2000
ACM
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...
DAC
2004
ACM
16 years 3 days ago
2004
ACM
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, w...
DAC
1999
ACM
16 years 3 days ago
1999
ACM
GLVLSI
2003
IEEE
15 years 4 months ago
2003
IEEE
In this paper, we discuss a methodology to design and synthesize analog CMOS components such as RF amplifiers. The inputs of the synthesis tool are the circuit specifications desc...
SBCCI
2006
ACM
15 years 5 months ago
2006
ACM
This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimizatio...