1217 search results - page 49 / 244 » Uncertainty-aware circuit optimization |
ASPDAC
2006
ACM
15 years 5 months ago
2006
ACM
With shrinking technology, the timing variation of a digital circuit is becoming the most important factor while designing a functionally reliable circuit. Gate sizing has emerged...
ISCAS
2003
IEEE
15 years 4 months ago
2003
IEEE
The effect of shield structures for local wirings of analog integrated circuits on crosstalk is determined by electromagnetic simulation. The crosstalk of parallel wirings is redu...
TCAD
2002
14 years 10 months ago
2002
Abstract--This paper investigates the application of simultaneous retiming and clock scheduling for optimizing synchronous circuits under setup and hold constraints. Two optimizati...
DATE
2005
IEEE
15 years 4 months ago
2005
IEEE
This paper presents the novel idea of multi-placement structures, for a fast and optimized placement instantiation in analog circuit synthesis. These structures need to be generat...
ARITH
2009
IEEE
15 years 6 months ago
2009
IEEE
Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open and largely unsolved problem, espec...