1217 search results - page 53 / 244 » Uncertainty-aware circuit optimization |
ASYNC
2007
IEEE
15 years 5 months ago
2007
IEEE
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. Howev...
ICCD
2000
IEEE
15 years 8 months ago
2000
IEEE
This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating of the ground bounce is presen...
ISLPED
2004
ACM
15 years 4 months ago
2004
ACM
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...
DATE
2010
IEEE
15 years 4 months ago
2010
IEEE
We present a framework and control policies for optimizing dynamic control of various self-tuning parameters over lifetime in the presence of circuit aging. Our framework introduc...
DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
This paper describes a systematic approach that facilitates yield improvement of integrated circuits at the post-manufacture stage. A new Configurable Analogue Transistor (CAT) st...