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» Uncertainty-aware circuit optimization
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ICCAD
1997
IEEE
69views Hardware» more  ICCAD 1997»
15 years 3 months ago
Speeding up technology-independent timing optimization by network partitioning
Technology-independenttimingoptimizationis animportantproblem in logic synthesis. Although many promising techniques have been proposed in the past, unfortunately they are quite s...
Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita
TCAD
2008
172views more  TCAD 2008»
14 years 11 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
APPROX
2008
Springer
190views Algorithms» more  APPROX 2008»
15 years 1 months ago
The Complexity of Local List Decoding
We study the complexity of locally list-decoding binary error correcting codes with good parameters (that are polynomially related to information theoretic bounds). We show that co...
Dan Gutfreund, Guy N. Rothblum
DSN
2011
IEEE
13 years 11 months ago
Cross-layer resilience using wearout aware design flow
—As process technology shrinks devices, circuits experience accelerated wearout. Monitoring wearout will be critical for improving the efficiency of error detection and correctio...
Bardia Zandian, Murali Annavaram
ICCAD
1994
IEEE
117views Hardware» more  ICCAD 1994»
15 years 3 months ago
Optimal latch mapping and retiming within a tree
We propose a technology mapping algorithm that takes existing structural technology-mapping algorithms based on dynamic programming [1,3,4] and extends them to retime pipelined cir...
Joel Grodstein, Eric Lehman, Heather Harkness, Her...