1217 search results - page 61 / 244 » Uncertainty-aware circuit optimization |
ASPDAC
2007
ACM
15 years 3 months ago
2007
ACM
Abstract-- In this paper we present the Statistical Retimingbased Timing Analysis (SRTA) algorithm. The goal is to compute the timing slack distribution for the nodes in the timing...
ASPDAC
2007
ACM
15 years 3 months ago
2007
ACM
Clock skew scheduling is a technique that intentionally introduces skews to memory elements to improve the performance of a sequential circuit. It was shown in [21] that the full ...
EUROGP
2000
Springer
15 years 2 months ago
2000
Springer
1 The function level evolvable hardware approach to synthesize the combinational multiple-valued and binary logic functions is proposed in rst time. The new representation of logic...
DATE
2007
IEEE
15 years 5 months ago
2007
IEEE
One of the main tasks in analog design is the sizing of the circuit parameters, such as transistor lengths and widths, in order to obtain optimal circuit performances, such as hig...
DSD
2007
IEEE
15 years 5 months ago
2007
IEEE
During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small ...