1217 search results - page 69 / 244 » Uncertainty-aware circuit optimization |
BIBE
2008
IEEE
15 years 5 months ago
2008
IEEE
Abstract-The aim of this work is to compare some deterministic optimization algorithms and evolutionary algorithms on parameter estimation in a biological circuit design problem: t...
ICCAD
2000
IEEE
15 years 3 months ago
2000
IEEE
This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timing-critical paths in a circuit. First, a continuous-variable delay model that ...
ETS
2006
IEEE
15 years 5 months ago
2006
IEEE
— Accurate generation of circuit specifications from test signatures is a difficult problem, since analytical expressions cannot precisely describe the nonlinear relationships ...
DATE
2006
IEEE
15 years 5 months ago
2006
IEEE
—Optimizing sequential cycles is essential for many types of high-performance circuits, such as pipelines for packet processing. Retiming is a powerful technique for speeding pip...
DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
Core-based system-on-chips (SoCs) fabricated on threedimensional (3D) technology are emerging for better integration capabilities. Effective test architecture design and optimizat...