1217 search results - page 70 / 244 » Uncertainty-aware circuit optimization |
ICCD
2004
IEEE
15 years 8 months ago
2004
IEEE
— In this paper, we approach the gate sizing problem in VLSI circuits in the context of increasing variability of process and circuit parameters as technology scales into the nan...
SBCCI
2005
ACM
15 years 4 months ago
2005
ACM
In this work the design of radiofrequency CMOS circuit blocks in the 910MHz ISM band, while biasing the MOS transistor in the moderate inversion region, is analyzed. An amplifier ...
FPGA
2008
ACM
15 years 23 days ago
2008
ACM
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
DAC
2003
ACM
15 years 4 months ago
2003
ACM
We present a new technique to examine the trade-off regions of a circuit where its competing performances become “simultaneously optimal”, i.e. Pareto optimal. It is based on ...
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DATE
2000
IEEE
15 years 3 months ago
2000
IEEE
Pass Transistor Logic has attracted more and more interest during last years, since it has proved to be an attractive alternative to static CMOS designs with respect to area, perf...