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» Uncertainty-aware circuit optimization
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DAC
2006
ACM
16 years 5 days ago
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors i...
John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S....
FPGA
2010
ACM
182views FPGA» more  FPGA 2010»
14 years 9 months ago
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs
Metastability is a phenomenon that can cause system failures in digital circuits. It may occur whenever signals are being transmitted across asynchronous or unrelated clock domain...
Doris Chen, Deshanand Singh, Jeffrey Chromczak, Da...
ISQED
2006
IEEE
78views Hardware» more  ISQED 2006»
15 years 5 months ago
Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines
Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper develops closed-form models to predict the dela...
Andrew Havlir, David Z. Pan
PIMRC
2010
IEEE
14 years 9 months ago
Optimal transmission rate for ultra low-power receivers
In many wireless systems, the energy consumed by the receiver is significantly larger than the energy consumed by transmitter, possibly even by orders of magnitudes. This paper der...
J. H. C. van den Heuvel, Jean-Paul M. G. Linnartz,...
DFT
1999
IEEE
131views VLSI» more  DFT 1999»
15 years 3 months ago
Optimal Vector Selection for Low Power BIST
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...
Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaud...