Sciweavers

1217 search results - page 83 / 244
» Uncertainty-aware circuit optimization
Sort
View
DATE
2002
IEEE
102views Hardware» more  DATE 2002»
15 years 4 months ago
Improving Placement under the Constant Delay Model
In this paper, we show that under the constant delay model the placement problem is equivalent to minimizing a weighted sum of wire lengths. The weights can be efficiently compute...
Kolja Sulimma, Wolfgang Kunz, Ingmar Neumann, Luka...
IACR
2011
212views more  IACR 2011»
13 years 11 months ago
Fully Homomorphic Encryption without Bootstrapping
We present a radically new approach to fully homomorphic encryption (FHE) that dramatically improves performance and bases security on weaker assumptions. A central conceptual con...
Zvika Brakerski, Craig Gentry, Vinod Vaikuntanatha...
ATS
1997
IEEE
89views Hardware» more  ATS 1997»
15 years 3 months ago
Guaranteeing Testability in Re-encoding for Low Power
This paper considers the testability implications of low power design methodologies. Low power and high testability are shown to be highly contrasting requirements, and an optimiz...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Mau...
DAC
2009
ACM
16 years 7 days ago
Statistical reliability analysis under process variation and aging effects
Circuit reliability is affected by various fabrication-time and run-time effects. Fabrication-induced process variation has significant impact on circuit performance and reliabilit...
Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan...
DAC
2006
ACM
16 years 6 days ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...