1217 search results - page 86 / 244 » Uncertainty-aware circuit optimization |
DAC
2009
ACM
15 years 6 months ago
2009
ACM
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
103
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ISCAS
2006
IEEE
15 years 5 months ago
2006
IEEE
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...
DAC
2000
ACM
16 years 7 days ago
2000
ACM
Contemporary microprocessors implement many iterative algorithms. For example, the front-end of a microprocessor repeatedly fetches and decodes instructions while updating interna...
144
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Lecture Notes
VLSI (Very Large Scale Integration) CMOS (Complementary Metal Oxide Semiconductor) technology is the main driver of our digital revolution. The goals of these lecture are to learn ...
DFT
1999
IEEE
15 years 3 months ago
1999
IEEE
This paper describes the yield estimation approach to layout scaling of submicron VLSI circuits. The presented method makes it feasible to find scaling factor of the IC design whi...