1217 search results - page 8 / 244 » Uncertainty-aware circuit optimization |
ARCS
2006
Springer
15 years 1 months ago
2006
Springer
State-of-the-art technologies in very large scale integration (VLSI) allow for the realization of gates with varying energy consumptions and hence delays (i.e., processing speeds) ...
ISLPED
1995
ACM
15 years 29 days ago
1995
ACM
Thispaper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor lay...
ICCAD
1998
IEEE
15 years 1 months ago
1998
IEEE
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
Reliability of nanometer circuits is becoming a major concern in today’s VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft erro...
DAM
2007
14 years 9 months ago
2007
In hardware design, it is necessary to simulate the anticipated behavior of the integrated circuit before it is actually cast in silicon. As simulation procedures are long due to ...