1217 search results - page 90 / 244 » Uncertainty-aware circuit optimization |
DATE
2005
IEEE
2005
IEEE
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction
15 years 4 months ago
This paper presents a design flow for an improved selective multi-threshold(Selective-MT) circuit. The Selective-MT circuit is improved so that plural MT-cells can share one switc...
ISCAS
2003
IEEE
15 years 4 months ago
2003
IEEE
A closed form expression for the rise time of a gate driving a distributed RLC line is introduced that is within 8% of dynamic circuit simulations for a wide range of RLC loads. I...
DM
2002
14 years 11 months ago
2002
A dual-eulerian graph is a plane graph which has an ordering defined on its edge set which forms simultaneously an Euler circuit in the graph and an euler circuit in the dual grap...
ITC
1999
IEEE
15 years 3 months ago
1999
IEEE
A high-level built-in self-test (BIST) synthesis involves several tasks such as system register assignment, interconnection assignment, and BIST register assignment. Existing high...
ICCAD
1998
IEEE
15 years 3 months ago
1998
IEEE
Abstract Althoughtremendousadvanceshave been accomplished in logic synthesis in the past two decades, in some cases logic synthesis still cannot attain the improvements possible by...