Sciweavers

1217 search results - page 99 / 244
» Uncertainty-aware circuit optimization
Sort
View
ISQED
2006
IEEE
176views Hardware» more  ISQED 2006»
15 years 10 months ago
Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages
— A new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented in this paper for simultaneously reducing active and standby mode power...
Zhiyu Liu, Volkan Kursun
118
Voted
DAC
1999
ACM
15 years 8 months ago
On ILP Formulations for Built-In Self-Testable Data Path Synthesis
In this paper, we present a new method to the built-in selftestable data path synthesis based on integer linear programming (ILP). Our method performs system register assignment, ...
Han Bin Kim, Dong Sam Ha, Takeshi Takahashi
CCS
2010
ACM
15 years 4 months ago
TASTY: tool for automating secure two-party computations
Secure two-party computation allows two untrusting parties to jointly compute an arbitrary function on their respective private inputs while revealing no information beyond the ou...
Wilko Henecka, Stefan Kögl, Ahmad-Reza Sadegh...
EUROCRYPT
2012
Springer
13 years 6 months ago
Fully Homomorphic Encryption with Polylog Overhead
We show that homomorphic evaluation of (wide enough) arithmetic circuits can be accomplished with only polylogarithmic overhead. Namely, we present a construction of fully homomorp...
Craig Gentry, Shai Halevi, Nigel P. Smart
DAC
2004
ACM
16 years 5 months ago
Worst-case circuit delay taking into account power supply variations
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm