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ICPP
2003
IEEE
15 years 9 months ago
Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores
In chip-multiprocessors (CMPs), the number of cores and the issue width of each core presents an important design trade-off to balance the amount of TLP and ILP between multi-thre...
Magnus Ekman, Per Stenström
DATE
2004
IEEE
135views Hardware» more  DATE 2004»
15 years 7 months ago
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
Francesco Menichelli, Mauro Olivieri, Luca Benini,...
DATE
2008
IEEE
101views Hardware» more  DATE 2008»
15 years 10 months ago
Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography
Madhura Purnaprajna, Christoph Puttmann, Mario Por...
IPPS
2006
IEEE
15 years 10 months ago
Leakage-aware multiprocessor scheduling for low power
Pepijn J. de Langen, Ben H. H. Juurlink