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IISWC
2008
IEEE
14 years 20 days ago
Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
Clay Hughes, Tao Li
ASPLOS
2004
ACM
13 years 11 months ago
Compiler orchestrated prefetching via speculation and predication
This paper introduces a compiler-orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. ...
Rodric M. Rabbah, Hariharan Sandanagobalane, Mongk...
ISCA
1996
IEEE
124views Hardware» more  ISCA 1996»
13 years 10 months ago
MGS: A Multigrain Shared Memory System
Parallel workstations, each comprising 10-100 processors, promise cost-effective general-purpose multiprocessing. This paper explores the coupling of such small- to medium-scale s...
Donald Yeung, John Kubiatowicz, Anant Agarwal
PLDI
2010
ACM
13 years 11 months ago
A GPGPU compiler for memory optimization and parallelism management
This paper presents a novel optimizing compiler for general purpose computation on graphics processing units (GPGPU). It addresses two major challenges of developing high performa...
Yi Yang, Ping Xiang, Jingfei Kong, Huiyang Zhou
IISWC
2006
IEEE
14 years 9 days ago
Performance Characterization of SPEC CPU2006 Integer Benchmarks on x86-64 Architecture
— As x86-64 processors become the CPU of choice for the personal computer market, it becomes increasingly important to understand the performance we can expect by migrating appli...
Dong Ye, Joydeep Ray, Christophe Harle, David R. K...