402 search results - page 13 / 81 » Understanding transactional memory performance |
HASE
2007
IEEE
15 years 3 months ago
2007
IEEE
Systems such as software transactional memory and some exception handling techniques use transactions. However, a typical limitation of such systems is that they do not allow syst...
IISWC
2009
IEEE
15 years 4 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
PPL
2010
14 years 7 months ago
2010
We present the Input Acceptance of Transactional Memory (TM). Despite the large interest for performance of TMs, no existing research work has investigated the impact of solving a...
ISAAC
2009
Springer
15 years 4 months ago
2009
Springer
Abstract. In a multicore transactional memory (TM) system, concurrent execution threads interact and interfere with each other through shared memory. The less interference a progra...
JPDC
2010
14 years 7 months ago
2010
Transactional Memory (TM) is a promising abstraction as it hides all synchronization complexities from the programmers of concurrent applications. More particularly the TM paradig...