402 search results - page 43 / 81 » Understanding transactional memory performance |
116
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DAC
2008
ACM
16 years 2 months ago
2008
ACM
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
117
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HPDC
2008
IEEE
15 years 8 months ago
2008
IEEE
Advances in virtualization technology have focused mainly on strengthening the isolation barrier between virtual machines (VMs) that are co-resident within a single physical machi...
118
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HPCA
2000
IEEE
15 years 5 months ago
2000
IEEE
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
115
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HPCC
2005
Springer
15 years 7 months ago
2005
Springer
In this paper we present an exhaustive evaluation of the memory subsystem in a chip-multiprocessor (CMP) architecture composed of 16 cores. The characterization is performed making...
139
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ISCA
2011
IEEE
14 years 5 months ago
2011
IEEE
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...