402 search results - page 64 / 81 » Understanding transactional memory performance |
HOTOS
2007
IEEE
15 years 1 months ago
2007
IEEE
We propose a new concurrent programming model, Automatic Mutual Exclusion (AME). In contrast to lock-based programming, and to other programming models built over software transac...
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SIGMETRICS
1996
ACM
15 years 1 months ago
1996
ACM
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
LCTRTS
2010
Springer
15 years 4 months ago
2010
Springer
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
CSMR
1999
IEEE
15 years 1 months ago
1999
IEEE
Maintenance activities are made more difficult when pointers are heavily used in source code: the programmer needs to build a mental model of memory locations and of the way they ...
MTA
2006
14 years 9 months ago
2006
Abstract There are increasing demands on portable communication devices to run multimedia applications. ISO (an International Organization for Standardization) standard MPEG-4 is a...