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» Understanding transactional memory performance
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ISCA
2006
IEEE
142views Hardware» more  ISCA 2006»
15 years 3 months ago
Bulk Disambiguation of Speculative Threads in Multiprocessors
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
Luis Ceze, James Tuck, Josep Torrellas, Calin Casc...
OSDI
1996
ACM
14 years 10 months ago
Dealing with Disaster: Surviving Misbehaved Kernel Extensions
Today's extensible operating systems allow applications to modify kernel behavior by providing mechanisms for application code to run in the kernel address space. The advanta...
Margo I. Seltzer, Yasuhiro Endo, Christopher Small...
DATE
2003
IEEE
132views Hardware» more  DATE 2003»
15 years 2 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...
102
Voted
TC
2002
14 years 9 months ago
Multiversion Data Broadcast
Broadcasting provides an efficient means for disseminating information in both wired and wireless setting. In this paper, we propose a suite of broadcast organization schemes for ...
Evaggelia Pitoura, Panos K. Chrysanthis
LISA
2008
14 years 11 months ago
Topnet: A Network-aware top(1)
System administrators regularly use the top utility for understanding the resource consumption of the processes running on UNIX computers. Top provides an accurate and real-time d...
Antonis Theocharides, Demetres Antoniades, Michali...